In recent years, with the increase of pixels and the reduction of chip sizes, various imaging devices with reduced pixel sizes have been developed. The following describes a conventional solid-state imaging device with reference to Patent Literature 1 (PLT 1).
FIG. 24 is a plan view of a pixel array part in a conventional solid-state imaging device. In this figure, in each of pixels which are two-dimensionally arranged, a photodiode (corresponding one of PD11 to PD44) and a transfer gate (corresponding one of TG11 to TG44) are arranged. Two photodiodes adjacent in a vertical direction (up-down direction) share an output circuit that includes a floating junction FJ, a reset transistor RS, and a drive transistor D. In the output circuit, the floating junction FJ is connected to a gate of the drive transistor D.
Each of the transfer gates TG11 to TG14, TG21 to TG24, TG31 to TG34, and TG41 to TG44 is connected to a corresponding one of read lines LTG1 to LTG4 extending in a horizontal direction (left-right direction). A gate of each of the reset transistors RS is connected to a corresponding one of reset lines RSL01 to RSL45 extending in the horizontal direction. A drain of each of the drive transistors D and a drain of each of the reset transistors RS are connected to a corresponding one of reset drains RD extending in the vertical direction. A source of each of the drive transistors D is connected to a corresponding one of signal lines S1 to S4 extending in the vertical direction.
In the solid-state imaging device according to PLT 1, a plurality of unit cells each including two photodiodes adjacent in the vertical direction are arranged in a check-like pattern, and each of the output circuits is provided between each pair of unit cells adjacent in the vertical direction. As a result, the solid-state imaging device according to PLT 1 enhances integration in the horizontal direction.